The v2.0+EDR Bluetooth SOC architecture for multimedia

This paper presents a Bluetooth system on chip (SOC) architecture for multimedia applications. The SOC includes all necessary baseband-parts, RF-parts, a sub-band codec (SBC) and an application processor to achieve a Bluetooth specification v2.0+EDR (enhanced data rate). Dual bus architecture is selected to improve data transmission efficiency between a baseband and a system bus. The receiver uses an optimized low-IF (1.5 MHz) architecture which is trade-off between power and performance on CMOS technology. The transmitter uses a direct up conversion architecture. This chip occupies a die size of 28 mm/sup 2/ in a 0.18 /spl mu/m CMOS. This chip and a flash memory are put into multi chip package (MCP). The maximum current consumption of the total chip is 65 mA at the TX mode. The internal supply voltages of RF- and digital-parts are 1.8 V. First measurement results meet most of the Bluetooth specification v2.Q+EDR and show the suitability of the presented single-chip concept.