A 48 channel pulse shape digitizer with DSP

A 48 channel, 40-65 MS/sec., 10 bit pulse shape digitizer card has been designed in the VME-6U form factor. The design uses 6 octal Flash Analog to Digital Converter (FADC) chips (ADS5121 or ADS5122) from Texas Instruments. The FADCs are read out by 6 Altera Cyclone FPGAs. A 7th FPGA is used to collect and merge the event fragments. The present firmware includes trigger latency buffers, waveform segment buffers, real-time digital filtering, time stamp generation, amplitude evaluation, event formatting and buffering, plus a simple VME A24D32 interface. The design also includes a source synchronous bi-directional serial LVDS link for the interconnection of the modules to a large system. The first version of the module is designed for an R&D test readout system connected to a few hundred drift chamber cathode pads or TPC cathode/anode pads. The final version is intended for the readout of the KOPIO preradiator cathode drift chamber pads (/spl sim/75000 channels). This version will only have the LVDS interconnect. The present design using off-the- shelf commercial components is an interesting alternative to an ASIC approach for intermediate size readout system. It occupies about 3 times the area of an equivalent ASIC system, and has comparable power dissipation. In its present form, the development version of the module can be useful as a general purpose waveform digitizer and DSP with its high density (48 channels per single width VME module) at a relatively low cost per channel.