Neural-network-based parasitic modeling and extraction verification for RF/millimeter-wave integrated circuit design

This paper reports an interconnect modeling approach for RF and millimeter-wave integrated circuits (ICs) using neural network models and a novel parasitic extraction verification procedure using automatically generated test structures. The effects of the parasitics in RF/millimeter-wave ICs are investigated with special focus on the parasitic inductances, since they are not evaluated by most of the commercially available extraction tools. State-of-the-art silicon-based multilayer RF process parameters are utilized to extract the resistive, the capacitive, and the inductive components of the layout interconnects. Neural network models are developed using electromagnetic (EM) simulation results of a set of passive interconnect structures. In addition, an automated layout generation methodology is used for the verification of the parasitic extraction methodologies. The proposed verification approach is demonstrated using automatically generated passive test structures and ring oscillators. The effects of parasitics are also investigated in voltage-controlled oscillators (VCOs) and amplifiers for millimeter-wave applications, and the neural models are verified using 30-GHz VCO measurement results. Hence, we present a complete modeling report of layout interconnect parasitics in RF/millimeter-wave integrated circuits as well as a novel verification procedure to validate non-EM analytical or neural models.