SOPC design for implementation of overcurrent relay

Design for implementation of an overcurrent relay as a system on programmable chip (SOPC) is presented. FPGA (field programmable gate arrays) is used for the system on chip (SOC) application to achieve a SOPC for the proposed design. The design is suitable for distribution or sub-transmission networks and can behave as extreme inverse or very inverse type of time overcurrent relay. The proposed relay follows standard inverse-time characteristics according to IEEE standard C37.112-1996. The details of hardware and software used for the design implementation are presented. Performance of the designed relay has been checked; the results from tests performed are also included in the paper.