A Compact Sequential Classifier for Digital Implementations

A simple and compact architecture for pattern classification is proposed and modeled. The architecture is a simplification of a kernel type classifier where kernel functions are selected as addressed of a RAM storing the coefficients encoding the learned problem. In our architecture the sorter is replaced with a much simpler to implement shift register and counting device. A fast learning scheme is proposed, ensuring a single-epoch training. The proposed classifier has no multipliers and thus it is extremely convenient for compact hardware implementations required by various low power intelligent systems. Despite its simplicity our architecture proves capable to perform comparably well with standard classifiers for most of the benchmark problems.