FPGA Implementation of Infomax BSS Algorithm with Fixed-Point Number Representation

Blind source separation (BSS) has promising applications in many fields such as communications and biomedical engineering. It is often necessary to realize the BSS algorithm in real time. In this paper field programmable gate arrays (FPGA) is used to implement the information-maximization (Infomax) algorithm of BSS with a fixed-point number representation. A system design of the Infomax BSS algorithm in the case of 2 inputs and 2 outputs is presented by using the Quartus II, the DSP builder and the Simulink. Compared with ASIC design, FPGA implementation has many advantages including short development time, convenient design platforms and low costs