Design practices and issues for simultaneous switching noise

This paper describes the modeling and the analysis methodology to evaluate simultaneous switching noise (SSN) for the combined system of the package with the 4-layer printed circuit board (PCB), which the 64 simultaneous switching outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit technique is easy to apply in the chip design instead of using embedded capacitors in the package's substrate. If the chip design applies both the skew control circuits for each data-signal group and slew-rate controlled output driver, SSN can keep within 5 percent of operational voltage based on the design practices and simulation results.