Thermomechanical design for reliability of WLPs with compliant interconnects

A wafer level packaging technology ELASTec/spl reg/ has been developed; which uses a resilient bump contact system. The advantages are twofold; because on the one hand the elastic contact system simplifies wafer probing and on the other hand the elastic interconnects allow an increase in board level reliability. Excessive solder bump straining caused by the mismatch of thermal expansion coefficients (CTE) between silicon and organic board materials can be avoided because of the compliance of the contact system, which can take over the main part of the mismatch deformation. Since the electrical connection is made by an electrodeposited copper/nickel redistribution layer (RDL), placed on top of the bump surface, other failures risks than solder fatigue emerge which were avoided by parametric studies using finite element analyses (FEA). The thermo-mechanical characteristics like stress-strain behavior and fatigue resistance of the RDL metallic films are the most important parameters for reliability predictions by FEA, discussed in some detail. The FEA based prediction that the fatigue performance of a spiral RDL layout is superior is proven experimentally and other reliability test data is provided.