Field-configurable test structure array (FC-TSA): enabling design for monitor, model and manufacturability

This work is designated to provide a common frame work of test chip design for technology development and process routine monitor, called as field-configurable test structure array (FC-TSA), which can accommodate and test the various types of test structures including transistors, diodes, and resistors. To minimize the probe-pad number and fully utilize area to maximize the area design efficiency, the memory addressing design scheme is implemented to select the device-under-test in a test chip. With the aid of using adjustable channel width of transmission gates, the input resistance of FC-TSA cell can be parameterized and configured to match with the parasitic resistance of various test structures, moreover, the background leakage could be minimized to meet with 1nA design specification. Two types of array test structures, 12/spl times/25 and 40/spl times/25, are implemented with generic logic process to demonstrate the design feasibility. The measurements of transistor set and process monitor test structures are reviewed and corresponding models are discussed.