Methodology for characterizing the impact of circuit layout, technology options, device engineering and temperature on the circuit power-delay characteristics

In this work, we present a methodology for characterizing the impact of circuit layout style, technology elements (low-k material, resist choice), device engineering and temperature on the circuit power-delay trade-off. We provide experimental results supported by modeling work, showing significant improvements in circuit speed at fixed power levels resulting from improvements in layout style and technology. For instance, the use of a more advanced resist at gate level leads to a 3/spl times/ reduction in static power dissipation at a given ring-oscillator (RO) delay or in other words close to a 10% improvement in the inverter delay for a similar static power dissipation.