Analysis and modeling of substrate impedance network in RF CMOS

This paper presents a new approach for analyzing and modeling the substrate impedance network in RF CMOS. Thanks to preliminary and proper de-embedding of known parasitics, the substrate network is directly identified. Using this approach on MOS transistors from 130 down to 65 nm technologies allows to point out the respective implications of the isolation layer and the surrounding well plug on high-frequency characteristics. Their impacts are studied and a new model is proposed.