Modeling of capacitor array mismatch effect in embedded CMOS CR SAR ADC

For CR SAR ADCs to be embedded in a system-on-chip, it becomes necessary to acquire how an underlying digital CMOS process that is used to implement the SOC would limit the performance of the ADC that consists of analog components such as the capacitor array. In this paper, we describe a novel modeling technique for the capacitor array mismatch effect on the attainable resolution of the CR SAR ADC. The proposed model is analytical in characteristics, which offers possible design trade-off among various factors including the appropriate selection of the capacitor array size, the CMOS process parameters, the layout structures, etc. and hence facilitates the co-design between the analog and digital circuits. The model is verified with MATLAB simulations. The results give some important insight into the tolerance behavior of the CR SAR ADC, which could form a theoretical basis for further design optimization.