A high-speed low-power D flip-flop

This paper proposes a new D flip-flop configuration based on differential cascode voltage switch with pass-gate logic. The circuit is able to reduce the transition time from the input to output. The flip-flop was implemented in 0.18 /spl mu/m CMOS technology. The flip-flop was simulated using HSPICE to assess the performance and was further evaluated by measurements on a test chip. The maximum operating frequency of the flip-flop is 5 GHz according to simulation. The test chip operates correctly at 3 GHz. This performance makes it one of the fastest flip-flops with a rail-to-rail input and voltage swing.