A 1-MHZ bandwidth 3.6-GHz 0.18-/spl mu/m CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise

A frequency synthesizer architecture capable of simultaneously achieving high closed-loop bandwidth and low output phase noise is presented. The proposed topology uses a mismatch compensated, hybrid phase/frequency detector and digital-to-analog converter (PFD/DAC) circuit to perform active cancellation of fractional-N quantization noise. When compared to a classical second-order /spl Sigma//spl Delta/ synthesizer, the prototype PFD/DAC synthesizer demonstrates >29 dB quantization noise suppression, without calibration, resulting in a fractional-N synthesizer with 1-MHz closed-loop bandwidth and -155 dBc/Hz phase noise at 20-MHz offset for a 3.6-GHz output. An on-chip band select divider allows the synthesizer to be configured as a dual-band (900 MHz/1.8 GHz) direct modulated transmitter capable of transmitting 271-kb/s GMSK data with less than 3 degrees of rms phase error.