Promote access speed of DRAM memory in net processor (NP) filed

Packet buffer allocate typically implemented using DRAM, which provides plentiful buffering at a reasonable cost. The problem we address is that a typical NP workload may be unable to utilize the peak DRAM bandwidth. Since the bandwidth of the packet buffer is often the bottleneck in the performance of a shared-memory packet switch. In this paper, we propose some ways to enhance average-case DRAM bandwidth. In modern DRAM, successive accesses falling within the same DRAM row are significantly faster than those falling across rows. If accesses to DRAM can be generated differently or reordered to take advantage of fast same-row accesses, peak DRAM bandwidth can be approached. This is the main point of this paper - row locality.