Asynchronous reconfigurable computing array design

We present a novel architecture of asynchronous reconfigurable computing array (ARCA) to seek the balance between performance and versatility. Advancing the completion detector of control circuit, a modified structure of asynchronous micropipeline based on DSDCVSL is discussed. The analysis and simulation of our ARCA have both resulted in high-performance and low-power consumption, and it can be used as an IP module integrated into a system on chip to built the reconfigurable computing platform.