An investigation on substrate current and hot carrier degradation at elevated temperatures for nMOSFETs of 0.13 /spl mu/m technology

In this report, nMOSFETs having 20 Aring and 32 Aring gate oxide thickness of 0.13 mum technology are used to investigate DC hot carrier reliability at elevated temperatures up to 125degC. The research also focused on the degradation of analog properties after hot carrier injection. Based on the results of experiments, the hot carrier degradation of I
_d,op
(defined based on analog application) is found to be the worst case from room temperature to 125degC. This result should be a valuable message for analog circuit designers. As to the reverse temperature effect, the substrate current (I
_b
) commonly accepted as the statues for monitoring the drain avalanche hot carrier (DAHC) effect should be modified since the drain current (I
_d
) degradation and I
_b
variations versus temperature have different trends. For the devices having gate oxide thinner than 20 Aring, we suggest that the worst condition in considering hot carrier reliability should be placed at elevated temperature