Detection of trap generation in high-k gate stacks

Constant voltage stress (CVS) combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO
₂
/HfO
₂
/TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-k gate stacks occurs primarily within the interfacial SiO
₂
layer (IL) on the as-grown "precursor" defects most likely caused by the overlaying HfO
₂
layer. These results point to the IL as a major focus for reliability improvement of high-k stacks