Sequential Circuit Delay Optimization Using Global Path Delays

We propose a novel sequential delay optimization technique based on network flow methods that simultaneously exploits delays on all paths in the circuit. We view the sequential circuit as an interconnection of path segments with pre-specified delays. Path segments are bounded by flip-flops, primary inputs or primary outputs. Recognizing that a delay optimizer can satisfy certain delay constraints more easily than others, we first propose a measure of difficulty for the delay optimizer. Our measure is based on explicit path delays to be satisfied by the delay optimizer. Also, our measure induces a partial order on the set of possible delay constraints. We then compute a set of delay constraints that is optimal with respect to our measure. The delay constraint set is optimal in the sense that it is the easiest constraint that can be specified to the delay optimizer. We formulate the delay constraint calculation problem as a minimum cost network flow problem. If the delay optimizer satisfies the optimal delay constraint set, then the resynthesized circuit may have several paths exceeding the desired clock period. However, we show that the resynthesized circuit can always be retimed to achieve the desired clock period. Experimental results on MCNC synthesis benchmarks show that our method improves the performance of circuits beyond what is achievable using optimal retiming and conventional combinational logic synthesis.