Cost Minimization of Partitions into Multiple Devices

This paper considers the problem of obtaining a minimum-cost partitioning of a large logic circuit into a collection of subcircuits implementable with devices selected from a given library. Each device in the library may have a different price, size, and terminal capacity. We propose a multi-way partitioning algorithm based on a recursive application of the Fiduccia-Mattheyses bipartitioning heuristic, extended to handle (a) the overall goal of the cost minimization and (b) the constraints reflecting the limitations on the capacity of FPGA chips. The experimental implementation of the proposed algorithm has exhibited a very encouraging performance, producing solutions close to the theoretical minima calculated for many benchmark circuits.