Routability-Driven Fanout Optimization

In this paper, we propose an efficient fanout optimization algorithm which improves circuit performance while honoring an order restriction on the fanouts. This order is derived from a companion placement of mapped circuit. By honoring the placement order we generate fanout trees that are free of internal edge crossings, resulting in improved routing and chip area. Our O(n/sup 3/) procedure which is based on an algorithm for constructing optimal alphabetic codes, is optimal for binary trees with monotone tree cost function. For nonbinary trees, we propose a set of rules which reduce size of the solution space while maintaining the optimality. We obtained an average of 14% improvement in chip area without a significant performance degradation as compared to the SIS fanout optimization tool.