Which junction for advanced CMOS?-theory, benchmark and predictions

In this paper, the theoretical considerations about junction design for advanced CMOS, to benchmark the most recent and advanced results, and make some predictions on the future needs are presented. Junction scaling is the key difference that grants better electrostatic integrity (essentially smaller DIBL) to SON/SOI and DG structures if compared with bulk. With the use of these structures, DIBL can be kept under control (<100 mV) down to 5-10 nm gate length.