Initial performance of the two-dimensional 4096-channel amplifier array

The two-dimensional 4096-channel amplifier array presented here was developed for a specific use in an area of X-ray astronomy. The amplifier array consists of a charge sensitive preamplifier, shaping amplifier, peak-hold circuit and analog multiplexor circuit together with a test-pulse circuit, analog-monitor circuit and digital-control circuit. The amplifier array was fabricated using a 0.25-/spl mu/m CMOS process of TSMC with options such as five-metal, double-poly, deep N-well and medium VT. The pixel circuit accommodates in the area of 200 /spl mu/m by 200 /spl mu/m with a power consumption of 150 /spl mu/W per channel. The power rails employed are /spl plusmn/1.25 V. The entire chip size is 16 mm by 16 mm, which accommodates the 4096 channels of the amplifier array. The noise level targeted is 1 keV (FWHM) with an appropriate CdTe pixel X-ray detector. In order to maintain the low-noise characteristics, special care was taken in the reinforcement of the power-supply rejection ratio, configuration of the bias circuit, elimination of D-to-A interference and even to eliminate the minor noise associated with the shaping amplifier. Eventually electronic noise was suppressed down to 100 electrons (rms) or less for a CdTe pixel X-ray detector. The other issue concerns the pixel-wise checkout of the amplifier array. The analog-monitor circuit multiplexes the preamplifier output, shaping-amplifier output and some subsidiary test points to be externally observed, and, then, every amplifier channel can be examined over the entire chip. The circuit design proceeded under the Open-IP project organized by ISAS, JAXA, with cooperation by related universities and research organizations.