Lattice-Mismatch and CMOS

We show that increasing the lattice constant on which CMOS electronics is constructed allows for an increasing electron and hole mobility in the NMOS and PMOS devices, respectively. This trend began with strained Si, and we have shown in research devices that compressed Ge combined with tensile Si can create previously unattainable high mobility MOS with high inversion charge. We also show that by increasing the lattice on Si to Ge, III-V electron channels become feasible, as well as integrated III-V optoelectronics. The core technology in advancing this lattice constant roadmap is dislocation and interface defect control