Adiabatic 4-2 compressors for low-power multiplier

This paper presents two adiabatic 4-2 compressors with complementary pass-transistor logic (CPAL). One is based on basic CPAL gates, while the other is realized using CPAL full adders. The architecture of an 8/spl times/8-bit adiabatic multiplier using adiabatic 4-2 compressors is described. The proposed compressors are verified using 0.25/spl mu/m TSMC CMOS process. The power consumption is significantly reduced, because the non-adiabatic energy loss of output loads has been eliminated using complementary pass-transistor logic for evaluation and transmission gates for energy-recovery. The simulation results show that the compressor using CPAL full adders consumes about 60% of the dissipated energy of the compressor using CPAL basic gates at 100MHz. Compared to the conventional CMOS implementation, the CPAL compressor attains energy savings of 85% to 95% for clock rates ranging from 25 to 150 MHz.