Bidirectional dynamic node low voltage swing domino logic

A new low voltage swing technique is presented in this paper for simultaneously reducing the active and standby mode power consumption and enhancing the noise immunity in domino logic circuits. The proposed circuit technique modifies both the upper and lower boundaries of the voltage swing at the dynamic node. Meanwhile, full voltage swing signals are maintained at the inputs and the outputs for high speed operation. The power supply and ground voltages are simultaneously optimized to minimize the power-delay product (PDP). The proposed technique reduces the PDP by up to 28% as compared to the standard full-swing circuits in a 45nm CMOS technology. The active mode power consumption is reduced by up to 32% due to the lower switching power required to charge/discharge the dynamic node. Furthermore, the noise immunity is enhanced by up to 59% as compared to the standard full-swing circuits. The bidirectional dynamic node low voltage swing technique also reduces the idle mode leakage power by up to 20% in the high fan-in domino gates. Furthermore, approximately a 3.9 /spl times/ reduction in leakage power consumption is offered as compared to a previously published low swing domino logic circuit technique in a 45nm CMOS technology.