Fast CMOS binary front end for silicon strip detectors at LHC experiments

We present design and test results of the front-end circuit developed in a 0.25 mum complementary metal-oxide semiconductor technology. The aim of this work is to study the performance of a deep submicron process in applications for fast binary front ends for silicon strip detectors. The channel comprises a fast transimpedance preamplifier working with an active feedback loop, two stages of the amplifier-integrator circuits providing 22 ns peaking time, and a two-stage differential discriminator. A particular effort has been made to minimize the current and the power consumption of the preamplifier, while keeping the required noise and timing performance. For a detector capacitance of 20 pF noise below 1500 e
^-
equivalent noise charge (ENC) has been achieved for 300 muA bias current in the input transistor, which is comparable with the levels achieved in the past for the front end using a bipolar input transistor. The total supply current of the front end is 600 muA and the power dissipation is 1.5 mW per channel. The offset spread of the comparator is below 3 mV rms