Impact of gate resistance on RF performance of fully depleted SOI MOSFET

We demonstrate that a metal T-gate can significantly lower the gate resistance and improve the RF performance in fully depleted SOI (FDSOI) MOSFETs. FETs with various combinations of number of gate fingers and finger width are compared, and the results show that T-gate provides increased layout flexibility. The effects of the gate resistance on the RF performance are studied and a simplified distributed-gate model is presented to improve the accuracy of the BSIM model for RF circuit simulations