A New Approach to Maximizing the Power Handling Capability in Recessed-Gate Silicon Carbide Static Induction Transistors

For a recessed gate SiC SIT, a new approach to solve a breakdown voltage specific on-resistance trade-off problem and consequently achieve an extremely high power capability was presented. Simulations were fully performed to analyze the influence of critical design parameters on the device power performance. They showed that the basic trade-off was successfully eliminated if the depth of a JFET diffusion layer was greater than 1.35 times the gate trench depth, due to the effective suppression of the JFET resistance. Consequently, the proposed device architecture showed much higher power capability than the conventional structure, suggesting that device power performance be maximized by implementing a JFET diffusion layer in a conventional SiC SIT, with a narrow half-width of a source region