Exploring logic block granularity in leakage tolerant FPGA

Exponential increase in static power has emerged as a critical challenge to FPGA architects in nanometer designs. The significant amount of underutilized resources both in spatial and temporal domain provides opportunities for effective power management. In this work, we carry out an in-depth trade-off analysis of various design goals in a power aware programmable architecture designed to mitigate standby leakage energy. We identify the optimum granularity of logic blocks at which standby leakage has to be controlled while optimizing trade-offs with other design goals.