Using shiftable content addressable memories to double memory capacity on embedded systems

We present a novel algorithm and architecture for memory compression using a series of shiftable content addressable memories (S-CAMs). The main contribution of this new algorithm is the use of a combination of an adaptive shared dictionary used across all memory pages, with one or more local adaptive dictionaries which are flushed after compressing a single memory page. Compression/decompression is capable of handling various types of memory content including application code and data. To this end, a fast compression/decompression architecture is necessary to move code and data from the non-compressed levels of memory hierarchy to the compressed ones and vice versa. Our technique takes advantage of fast parallel comparisons that can be achieved by S-CAMs to implement our dictionary based compression algorithm. Our results show memory reductions that are substantially better (more than doubling the available memory for certain applications) than existing CAM-based memory approaches such as X-Match Pro. These results have been achieved by using the newest embedded processor architectures such as the Xtensa platform that feature a dense instruction word encoding even without compression.