A low cost, high quality embedded array DFT technique for high performance processors

This paper describes a low cost, high quality array DFT technique that will save overall manufacturing test time by /spl sim/50%. This technique integrates a programmable on-die test generation engine into the direct access test (DAT) controller via the parallel DAT interfaces. It can be used to test different types of embedded arrays at system speed. It has been validated on an Intel/spl reg/ high performance microprocessor design.