Field programmable gate array (FPGA) for iterative code evaluation

Iterative codes such as low density parity check (LDPC) codes and turbo product codes (TPC) are of interest for data storage applications. To apply these codes to digital recording systems, two possible schemes are considered in this paper. In the first scheme, a single LDPC code of column weight j>2 is used to replace the Reed-Solomon (RS) code of the conventional channel. In the second scheme, an iterative code is used as the inner code and is concatenated with an outer RS code. Single parity check TPC code is considered for this scheme. We developed a high-throughput field programmable gate array (FPGA) platform to evaluate the error floor performance of LDPC codes and the error statistics of TPC codes in partial response (PR) channel with turbo equalization. High rate codes (rate 8/9 for LDPC code and rate 0.935 for TPC code) are evaluated for magnetic recoding application. The bit error rate (BER) performance of LDPC code down to 10/sup -10/ can be reached within 2 h using the FPGA platform. The TPC code error statistics are evaluated using about 10/sup 11/ bits at different signal-to-noise (SNR) levels. For practical implementation complexity and power consumption, 2 channel iterations and 2 TPC decoder iterations are employed. The results show that the gain by applying TPC code under 2 channel iterations and 2 TPC decoder iterations is marginal.