A very low-complexity space-time block decoder (STBD) ASIC for wireless systems

This paper presents a computationally efficient application-specific integrated circuit (ASIC) implementation for the decoding of space-time block codes (STBCs) . Alternative methods of evaluating the originally proposed maximum-likelihood decision metrics are explored at the algorithm and architectural level. At the algorithm level, unique decoding techniques are developed that result in computation savings of as much as 65%. At the architectural level, a low-computation symmetrical approach for the implementation of the proposed algorithm is presented. The proposed ASIC architecture offers considerable computation reductions leading to substantial power and area savings compared to a direct implementation of the original algorithm. The proposed architecture was realized in an ASIC referred to as the ST block decoder ASIC. The chip was fabricated using 0.18-/spl mu/m CMOS technology and occupies a core area of 0.25 mm/sup 2/. The ASIC architecture is highly scalable and can implement 2 /spl times/ 2, 8 /spl times/ 3, and 8 /spl times/ 4 STBCs with modulation formats ranging from binary-phase shift keying (BPSK) to 16 quadrature amplitude modulation (QAM), and can operate at any symbol rate up to 20 Mbaud. Depending on the mode of operation, the decoder power consumption ranges from 0.54 mW for 2 /spl times/ 2 BPSK systems to 1.89 mW for 8 /spl times/ 4 16-QAM systems.