A 9.2mW 528/66/50MHz monolithic clock synthesizer for mobile /spl mu/P platforms

A low-power monolithic clock synthesizer suitable for use in mobile /spl mu/P platforms is presented. Clock synthesis is accomplished using an all-Si RF LC reference oscillator that does not require an external frequency reference. Fabricated in 0.18/spl mu/m CMOS, the developed clock synthesizer demonstrates /spl plusmn/1% frequency accuracy over process, voltage, and 0-70/spl deg/C, exhibits 7.4/21/33ps/sub rms/ period jitter on 528/66/50MHz clock signals, and achieves a start-up latency of only 3.2/spl mu/s.