A 50 MS/s 12-bit CMOS pipeline A/D converter with nonlinear background calibration

A new background calibration method, based on stage error pattern estimation, is presented. The method corrects both linear and nonlinear errors. The procedure converges in a few ms and requires minimal hardware without the need of high-capacity ROM or RAM. The calibration procedure is tested on a 0.6 /spl mu/m CMOS pipeline ADC, which suffered from a high degree of nonlinear errors. The calibration gives improvements of 18dB and 28dB for SNR and SFDR, respectively, at the sampling rate of 50MSample/s. The calibrated ADC achieves SNR of 70.9dB and SFDR of 82.0dB at 50MSample/s, which results in a resolution of about 12 bits.