Pipeline scheduling for array based reconfigurable architectures considering interconnect delays

Pipelining is a powerful technique to achieve high performance design. Nowadays, in deep-submicron (DSM) process era, interconnect delay is becoming so dominant that it can no longer be neglected in high level synthesis. Considering interconnect delays in pipeline scheduling can be a promising technique to improve the design performance in the DSM era. However, until now there are few researches on this topic. In this paper, we present an interconnect aware pipeline scheduling algorithm for array based reconfigurable architectures. The proposed algorithm is able to perform scheduling, placement and routing simultaneously under the modulo scheduling constraints. Experimental results show that our algorithm can improve performance by 47.26% on average compared to those that use pipelining technique but do not consider interconnect delays.