An area-efficient VLSI architecture for Reed-Solomon decoder

In this paper, the known decoding procedure for Reed-Solomon (RS) code is analyzed in the way of vector operations that are suitable for VLSI implementation and pipelining. Then, a new area-efficient architecture for RS decoder is proposed. The new architecture can improve the reuse rate of main computation unit, reduce the hardware complexity and delete the redundancy circuit. The results show that the total number of gates of the proposed RS (204,188) decoder is about 27,000 gates, which is about 39% smaller than the same kind of conventional ones. It has been integrated in a channel demodulation chip for high-definition television (HDTV) and the chip has been tested successfully in practice.