System-level BER test and jitter extraction of a 6.4Gbps parallel chip to chip bus on the first generation CELL/spl trade/ processor

At multi-gigahertz data rate, it is a very challenging task to have an accurate and reliable method to measure system performance, in particular, to account for the impact of both deterministic and random jitter. Such measurement method must be able to capture major jitter components without the need of long testing time as well as expensive testing hardware. In this paper, we extend our previous work (Madden, 2004) to extract system level jitter in terms of deterministic and random jitter and extrapolate to very low bit error rate for a 6.4Gbps parallel bus. To that end, we designed an error counter and a bit counter into our FlexIO/spl trade/ interface so that built-in self-test can be performed without the need for a bit error rate tester (BERT). In addition, all I/Os of the interface can be tested simultaneously. Finally, we demonstrate the accuracy of the proposed method by correlating with traditional direct jitter measurement method.