Design for stackability of flash memory devices based on thermal optimization

Convergence of computing and communications dictates building up rather than out. As consumers demand more functions in their hand-held devices, the need for more memory in a limited space is increasing. Over the past few years, die stacking has emerged as a powerful tool for satisfying challenging IC packaging requirements. As stacked packaging evolves into taller stacks, what issues do we face? Traditionally, chip stacking was carried out with dies of different sizes so the top die was always smaller than the bottom die to permit wire bonding of both. Today, it's common to see the stacking of same-size dies or a larger die over a smaller one. One way to accommodate a larger or same-size die on top is to place a spacer (a dummy piece of silicon) between the two. Then, the spacer lifts the top die just enough to allow wire bonding to the bottom die. Another way of stacking same size die is by placing the die in different orientation. This paper focuses on the thermal analysis and optimization of stacked die area array package. Thermal analysis was done on a 3-Die stacked FBGA package using FEM tool ANSYS 9.0. Optimization was then performed on a 3-Die stacked area array package using design explorer. Then the 3-Die stacked package was extended to 7-Die stacked package using ANSYS Workbench 9.0. Three different stack configurations (staggered, rotated and spacer die) with same die size were considered for comparison purposes. Optimization was done by varying seven die powers to get the best design for stackability based on thermal performance of the package.