Effect of scaling on stand-by current in PD-SOI pseudo-nMOS circuits

As technology is scaled, the leakage currents pose significant problems during active and stand-by modes of operation. This scenario leads us to re-evaluate less commonly used logic styles for future use. In this paper we consider the pseudo-nMOS logic circuits and evaluate the effect of scaling on the stand-by current in 130nm and 90nm PD-SOI technology.