FPGA implementation of modified radix 2 SRT division algorithm

The flexibility of field programmable gate arrays (FPGAs) can provide arithmetic intensive applications with the benefits of custom hardware but without the high cost of custom silicon implementations. In this paper, we present the adaptation of modified radix 2 division algorithm by Cquillan, et al. (1993) for lookup table based FPGAs implementation. For this modified scheme, the result digits and the residuals are computed concurrently and the computations in adjacent rows are overlapped. The implementation has been done with Xilinx technology and FPGA-Advantage CAD tools.