Design of a PLL based frequency synthesizer for multi-standard transceivers

In this paper, the architecture of a dual loop frequency synthesizer for both GSM and DECT standards is described. The implementation for the low frequency loop is presented. The performance of each stage is introduced. The PLL is implemented using CMOS 0.6/spl mu/m technology with power consumption of 1.7 mW and settling time of 40/spl mu/sec.