Comparison of a programmable DSP and FPGA implementation for a wavelet-based denoising algorithm

In this work the authors presented a field programmable gate array (FPGA) and a digital signal processor (DSP) implementations of an algorithm for real-time signal detection and denoising based on undecimated (stationary) wavelet packet transform (SWPT). The performance was compared in terms of operating clock frequencies, power consumption and signal-to-noise-ratio (SNR) due to finite word-length effects using a fixed-point arithmetics in the FPGA and floating-point in DSP. Finally the possibility of reconfiguration and extension is considered