Design of FGMOS log-domain filters

In this paper, design trade-offs for a CMOS implementation of low voltage low power logarithmic filters based on floating-gate-MOS transistors (FGMOS) are analysed. Limits for power consumption, power supply and cutoff frequency of a second order filter based on log-domain integrator architecture are found. The influence of capacitor matching in FGMOS structures on the nonlinear performance of the filter is investigated