Design and implementation of phase correlation based motion estimator

This paper describes an architecture for the efficient computation of motion estimation based on phase correlation (PC). The entire block has been implemented on a Virtex2 FPGA, and particular care has been posed on the throughput requirements in a video coding framework. These tight requirements lead to the need for high performance solutions for both the discrete Fourier transform (DFT) block and the vector normalization engine. The DFT stage has been implemented with a pipelined decimation in time (DIT) flow, while a multiplierless CORDIC-based structure is used for the vector normalization