Improvement of the current-voltage characteristics of a tunneling dielectric by barrier engineering by adopting an atomic-layer-deposited SiN layer for flash memory applications

In this paper new and superior characteristics of an atomic layer deposited (ALD) SiN layer and SiN/SiO/sub 2//SiN multi layers as gate dielectric for flash memory application are reported. Field-sensitive characteristics compared to SiO/sub 2/ were obtained by barrier profile engineering with a SiN/SiO/sub 2//SiN stack; a lower leakage current at a low field and a higher leakage current at a high field. The stacked dielectric layer showed F-N tunneling. However, the interfacial potential barrier profile was somewhat smoothed by chemical interaction between the individual layers. The interfacial trap density of this dielectric with an ALD SiN bottom layer was as low as 4/spl times/10/sup -10//cm/sup 2/eV near the mid-gap energy state, but the re-oxidation process degraded the interface quality. The degradation mechanism was studied using electrical analysis, XPS, and TEM.