Enhancement of data retention time in DRAM using step gated asymmetric (STAR) cell transistors

For the first time, we developed successfully the 512Mb DRAMs using step-gated-asymmetric (STAR) cell transistors with 90nm feature size. The STAR with step recessed channel depth of 40nm exhibits distinctly improved electrical characteristics such as BV/sub DS/, junction leakage and word-line capacitance (C/sub WL/), comparing to a conventional planar and recess-channel transistors of the same gate length. The two major merits using the STAR in DRAMs are about 200% improvement of data retention time and low costs of KrF lithography process rather than those of ArF lithography process. Moreover, this STAR technology is able to extend to sub-80nm by scaling STAR depth and width without increasing the concentration of substrate.