A 75dB image rejection IF-input quadrature sampling SC /spl Sigma//spl Delta/ modulator

Quadrature sampling of intermediate frequency (IF) signals is subject to the well-known problem of gain and phase mismatches between the in-phase (I) and quadrature (Q) paths of analog circuitry. This paper presents an IF-input quadrature-sampling switched-capacitor (SC) /spl Sigma//spl Delta/ modulator that circumvents the I/Q mismatch problem by time-sharing between the I and Q paths the critical components, namely, the sampling capacitors and the capacitors of the first-stage feedback digital-to-analog converter. Moreover, a clocking scheme insensitive to I/Q phase imbalance is used. A 3rd order lowpass single-loop 1-bit modulator has been designed and fabricated in a 0.35/spl mu/m CMOS process with an active area of 0.57mm/sup 2/. Experimental results show that the modulator achieves an image-rejection ratio (IRR) of greater than 75dB throughout a 100 kHz bandwidth.