A 3.33Gb/s (1200,720) low-density parity check code decoder

In this paper, a (1200,720) LDPC decoder based on an irregular parity check matrix is presented. For achieving higher chip density and less critical path delay, the proposed architecture features a data reordering such that only one specific data bus exists between message memories and computational units. Moreover, the LDPC decoder can also process two different codewords concurrently to increase throughput and datapath efficiency. After chip implementation, a 3.33Gb/s data rate is achieved with 8 decoding iterations in the 21.23mm/sup 2/ 0.18/spl mu/m silicon area. The other 0.13/spl mu/m chip with the 10.24mm/sup 2/ core can further reach a 5.92Gb/s data rate under 1.02V supply.